AI-native chip design house anchors the design pillar of OpenForge, compressing ASIC development cycles for verifiable compute.
BELLEVUE, WA, UNITED STATES, June 9, 2026 /EINPresswire.com/ — Future Intelligence Labs, Inc. (FiLabs), the AI-native chip design house, today announced a strategic partnership with OpenForge, the vertically integrated hardware coalition pioneering Cysic’s ComputeFi thesis. FiLabs joins OpenForge as a partner in its design pillar, applying its multi-agent AI platform to next-generation purpose-built hardware for zero-knowledge proof generation and verifiable AI inference.
The partnership marks OpenForge’s first engagement with an AI-native chip design house — and a direct challenge to the economics of traditional ASIC development. Conventional design houses typically require 12 to 18 months and $10M–$25M in non-recurring engineering costs per program. For ZK hardware companies, that ceiling has been the single biggest constraint on silicon velocity — even as demand for verifiable compute accelerates across rollups, AI inference, and decentralized applications.
FiLabs operates differently. As an AI-native design house, FiLabs takes end-to-end ownership of the chip design process — RTL, verification, and physical layout — using proprietary AI agents to execute what traditional design houses staff with large engineering teams. In early engagements, FiLabs has demonstrated up to 150× design-efficiency gains, 100% verification coverage on delivered modules, and project timelines compressed by roughly 50% at one-third the cost. The result is design-cycle compression from months to weeks on critical stages, without sacrificing the rigor required for production-grade cryptographic silicon.
“ComputeFi will only scale as fast as the silicon underneath it,” said Dr. Leo Fan, Founder and CEO of Cysic. “OpenForge is how we assemble that silicon supply chain — design, manufacturing, and distribution partners working in coordination rather than in series. FiLabs anchors the design side as our first AI-native partner, and the speed advantage they bring translates directly into faster, cheaper, more accessible verifiable compute for our network.”
“OpenForge is building the foundational hardware layer for verifiable compute — in a domain where every month of design-cycle compression compounds,” said Dr. Meng, CEO of FiLabs. “Cryptographic silicon is exactly the workload we were built for: high-complexity, high-stakes, and chronically underserved by legacy design houses.”
The engagement will initially focus on design exploration and verification for the next-generation ZK accelerator, with scope to extend across the broader silicon roadmap — including AI inference ASICs and the portable ZK Air form factor.
About FiLabs Future Intelligence Labs, Inc. (FiLabs) is building the AI-native chip design house for the next generation of silicon. By replacing traditional design-house infrastructure with orchestrated AI agents, FiLabs gives fabless and verticalized hardware teams access to full-stack chip design — faster, leaner, and without the NRE overhead that has defined the industry for decades. Learn more at: https://www.futureintelligencelab.ai
About OpenForge OpenForge is the vertically integrated hardware coalition pioneering Cysic’s ComputeFi thesis, bringing together design, manufacturing, and distribution partners to deliver purpose-built silicon for verifiable compute. By coordinating the full hardware supply chain under a single coalition, OpenForge compresses the path from architecture to deployment for ZK accelerators, AI inference ASICs, and emerging form factors. Learn more at https://openforge.one.
About Cysic Cysic is the leading ComputeFi network, combining custom ZK ASICs, high-throughput compute infrastructure, and a programmable Layer 1 blockchain to turn compute into a liquid, on-chain asset class. Backed by Polychain Capital, HashKey Capital, OKX Ventures, IDG, and Matrix Partners, Cysic powers verifiable compute for leading rollups and AI applications. Learn more at https://cysic.xyz/.
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